This invention relates to, and the following discussion assumes skill in, the design of integrated circuit chip floorplan, layout or topography.
In the design of very high performance integrated circuits, designers have to deal with multiple clock frequencies in the GHz frequency domain. Very often there is a primary frequency that drives most of the design and secondary frequencies used to drive selected parts of the design, such as for example an I/O interface. There are several design strategies to distribute these clock signals to their destinations. In one strategy the primary clock signal is distributed through a global clock distribution network to reach all the surface area of the chip, using a two-stage distribution network.
Other clock signals can be distributed in a similar fashion. However, if these signals are only used in specific areas of the design, such global distribution would be a waste of design resources. Furthermore, if these signals are sub-frequencies of the main clock signal, it is important to keep them linked to facilitate synchronization between the signals. One design technique for creating and distributing signals to drive portions of a design at different clock frequencies is to send a control signal from the clock source synchronized with the main clock. At the destination this signal is combined with the main clock signal, for example a frequency divider, to create the desired frequency. Synchronization between destinations at different locations on the chip is achieved by ensuring that the control signal reaches each destination at the same time independent of the location of the destinations. A design technique to ensure control signals are synchronized with the main clock signal is by using latches in the distribution of the control signals, the latches being controlled by the main clock signal.
The latch structures are known as Latch Distribution Trees (LDTs). In the present disclosure, new design approaches for LDTs are presented that allow design by construction of trees while reducing the load impact of such trees on the main clock distribution network. Furthermore, new approaches are introduced to distribute the load of LDTs on the main clock distribution network to help balancing clock skew. LDTs are sometimes identified as plats, and plats may be consolidated into macros drawn from a library of chip floorplan designs.